Design of large built-in self-test programmable logic arrays

Abstract

This paper presents a way to optimize design of large built-in self-test (BIST) programmable logic arrays (PLAs). These PLAs can be tested at clock speed with function independent test set. Hardware overhead of the design is low compared to other techniques. In the design, test pattern generators are simple shift registers connected in ring counter form. Response evaluator circuit is a signature analyzer. A two bit binary counter and two D flip-flops automate the design process and reduce the number of test control pins. The PLA can detect all stuck-at, crosspoint, bridging as well as stuck-open faults